1. Field of Invention
The present invention relates to a method for forming a semiconductor device. More particularly, the present invention relates to a method for forming a dielectric layer with a low dielectric constant (low-k).
2. Description of Related Art
In the current process of very large scale integration (VLSI), more than two metal layers are fabricated to satisfy the integration requirements. This is called multilevel interconnect. With the increase of integration and the shrinking device size in integrated circuits (IC), metal lines are increasingly closer so that an increasingly serious capacitance effect is induced between the two metal lines. As a result, the crosstalk between conductors and impedance in the circuit structure are increasingly serious so as to increase resistance capacitance time delay. Thus the circuit performance is degraded.
The resistance of conductive lines and a parasitic capacitance are crucial factors to affect the performance. Commonly one resolution is to choose metal material with a low resistance to reduce the resistance between the conductive lines. Another resolution is use of dielectrics with a low dielectric constant (low-k) to reduce the parasitic capacitance.
In the conventional art, a silicon oxide layer is formed between metal lines to serve as a dielectric layer. The method for forming the silicon oxide layer includes high density plasma chemical vapor deposition (HDP-CVD), or plasma enhanced chemical vapor deposition (PECVD) using tetra-ethyl-ortho-silicate (TEOS) as gas source. The dielectric constant of the silicon oxide layer is about 4.1. However, the dielectric constant 4.1 of the dielectric layer is not sufficient for use at the sub-half micro level of fabrication. As a result, a parasitic capacitance induced between conductive lines becomes more serious so as to increase a RC time delay, and reduce the performance.